As known, the majority of these devices, which are known in the literature as "Winner Take All" (WTA), are provided by means of architectures which exhibit a voltage-follower configuration and make use of inhibitor mechanisms operating among the calculation elements included in them.
A first known technical solution, shown in FIG. 1 and described in the article "Winner Take All Networks of O(N) Complexity," J. Lazzaro et al., Neural Inform Proc. Syst. 1:703-711, Denver, Colo., 1989, calls for the use of a selector device 1 comprising a plurality of circuit branches 2 operating in parallel and each including a first voltage follower transistor T1i and a second local positive feedback transistor T2i, where i=1,. . . j, . . . n.
The device I also comprises a total feedback line LN common to all the circuit branches 2.
Operation of the selector device 1 is as follows.
Each circuit branch 2 receives the input of a one-way current Ii and supplies output of a voltage Vi which represents the result of the selection process.
When the current Ii=max (Il,. . . In), the voltage Vi coincides with a logarithmic function of Ii, and if the current Ij&lt;&lt;Ii, the voltage Vj.about.0.
Although advantageous in some ways, this first solution exhibits diverse shortcomings.
Indeed, the device 1 does not provide any offset compensation and has a calculation time which depends on the number of elements making it up.
A second known technical solution is described in the article "A Scalable High-Speed Current-Mode Winner Take All Network for VLSI Neural Applications," Sean Smedley et al., IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications 42(5), 1995 which proposes a tree-structured circuit comprising a plurality of cells provided by using bipolar transistors integrated with a BICMOS technology.
Each cell receives at input two current signals I1 and I2 which are compared with each other to select the highest one.
The latter represents the input for a cell included in a subsequent layer of the tree structure and so on until there is obtained at output the higher input current signal.